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| #define SDHCI_POWER_CONTROL 0x29
static void sdhci_dumpregs(UINT32 base)
{
SDIOLOG_TRACE(": ============== REGISTER DUMP ==============\r\n");
SDIOLOG_TRACE(": DMA addr: 0x%08x | Version: 0x%08x\r\n",
sdio_readl(base, SD_SYSADDR_LOW_offset),
sdio_readw(base, SDHCI_HOST_VERSION));
SDIOLOG_TRACE(": Blk size: 0x%08x | Blk cnt: 0x%08x\r\n",
sdio_readw(base, SD_BLOCK_SIZE_offset),
sdio_readw(base, SD_BLOCK_COUNT_offset));
SDIOLOG_TRACE(": Argument: 0x%08x | Trn mode: 0x%08x\r\n",
sdio_readl(base, SD_ARG_LOW_offset),
sdio_readw(base, SD_TRANSFER_MODE_offset));
SDIOLOG_TRACE(": Present: 0x%08x | Host ctl: 0x%08x\r\n",
sdio_readl(base, SD_PRESENT_STAT_0_offset),
sdio_readw(base, SD_HOST_CTRL_offset));
SDIOLOG_TRACE(": Power: 0x%08x | Blk gap: 0x%08x\r\n",
sdio_readw(base, SDHCI_POWER_CONTROL), /*导致dump的地方*/
sdio_readw(base, SD_BGAP_CTRL_offset));
SDIOLOG_TRACE(": Wake-up: 0x%08x | Clock: 0x%08x\r\n",
sdio_readb(base, SDHCI_WAKE_UP_CONTROL),
sdio_readw(base, SD_CLOCK_CTRL_offset));
SDIOLOG_TRACE(": Timeout: 0x%08x | Int stat: 0x%08x\r\n",
sdio_readw(base, SD_SW_RESET_CTRL_offset),
sdio_readl(base, SD_NORM_INTR_STS_offset));
SDIOLOG_TRACE(": Int enab: 0x%08x | Sig enab: 0x%08x\r\n",
sdio_readl(base, SD_NORM_INTR_STS_EBLE_offset),
sdio_readl(base, SD_NORM_INTR_STS_INTR_EBLE_offset));
SDIOLOG_TRACE(": AC12 err: 0x%08x | Slot int: 0x%08x\r\n",
sdio_readw(base, SDHCI_ACMD12_ERR),
sdio_readw(base, SDHCI_SLOT_INT_STATUS));
SDIOLOG_TRACE(": Caps: 0x%08x | Max curr: 0x%08x\r\n",
sdio_readl(base, SDHCI_CAPABILITIES),
sdio_readl(base, SDHCI_MAX_CURRENT));
SDIOLOG_TRACE(": Command: 0x%08x | RX_CFG_REG:0x%08x\r\n",
sdio_readw(base, SD_CMD_offset),
sdio_readl(base,SDHCI_RX_CFG_REG));
SDIOLOG_TRACE("SDHCI_HOST_CTRL2: 0x%08x | PRESET_VALUE_FOR_SDR50:0x%08x",
sdio_readw(base, SDHCI_HOST_CTRL2),
sdio_readw(base, SDHCI_PRESET_VALUE_FOR_SDR50));
SDIOLOG_TRACE(": ===========================================\r\n");
}
|